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1 f e a t u r e s 3 . 3 v o l t s u p p l y 5 v t o l e r a n t i n p u t s a n d t t l c o m p a t i b l e o u t p u t s 2 5 6 x 2 5 6 c h a n n e l n o n - b l o c k i n g s w i t c h p r o g r a m m a b l e f r a m e i n t e g r i t y f o r w i d e b a n d c h a n n e l s a u t o m a t i c i d e n t i c a t i o n o f s t - b u s / g c i i n t e r f a c e b a c k p l a n e s p e r c h a n n e l t r i s t a t e c o n t r o l p a t e n t e d m e s s a g e m o d e n o n - m u l t i p l e x e d m i c r o p r o c e s s o r i n t e r f a c e a v a i l a b l e i n p l c c - 4 4 a n d s s o p - 4 8 p a c k a g e s p i n c o m p a t i b l e w i t h m t 8 9 8 5 d e v i c e l o w p o w e r c o n s u m p t i o n a p p l i c a t i o n s m e d i u m s i z e d i g i t a l s w i t c h m a t r i c e s h y p e r c h a n n e l s w i t c h i n g ( e . g . , i s d n h 0 ) s t - b u s / m v i p i n t e r f a c e f u n c t i o n s s e r i a l b u s c o n t r o l a n d m o n i t o r i n g c e n t r a l i z e d v o i c e p r o c e s s i n g s y s t e m s d a t a m u l t i p l e x e r d e s c r i p t i o n t h e m t 8 9 l 8 5 e n h a n c e d d i g i t a l s w i t c h d e v i c e i s a n u p g r a d e d 3 - v o l t v e r s i o n o f t h e m t 8 9 8 5 d i g i t a l s w i t c h . i t i s p i n c o m p a t i b l e w i t h t h e m t 8 9 8 5 a n d r e t a i n s a l l o f t h e m t 8 9 8 5 ' s f u n c t i o n a l i t y . t h e e n h a n c e d d i g i t a l s w t i c h i s d e s i g n e d f o r s w i t c h i n g p c m - e n c o d e d v o i c e o r d a t a , u n d e r m i c r o p r o c e s s o r c o n t r o l , i n d i g i t a l e x c h a n g e s , p b x s a n d a n y s t - b u s / m v i p e n v i r o n m e n t . i t p r o v i d e s s i m u l t a n e o u s c o n n e c t i o n s f o r u p t o 2 5 6 6 4 k b / s c h a n n e l s . e a c h o f t h e e i g h t s e r i a l i n p u t s a n d o u t p u t s c o n s i s t o f 3 2 6 4 k b i t / s c h a n n e l s m u l t i p l e x e d t o f o r m a 2 0 4 8 k b i t / s s t r e a m . a s t h e m a i n f u n c t i o n i n s w i t c h i n g a p p l i c a t i o n s , t h e d e v i c e p r o v i d e s p e r - c h a n n e l s e l e c t i o n b e t w e e n v a r i a b l e o r c o n s t a n t t h r o u g h p u t d e l a y s . t h e c o n s t a n t t h r o u g h p u t d e l a y f e a t u r e a l l o w s g r o u p e d c h a n n e l s s u c h a s i s d n h 0 t o b e s w i t c h e d t h r o u g h t h e d e v i c e m a i n t a i n i n g i t s s e q u e n c e i n t e g r i t y . t h e m t 8 9 l 8 5 i s i d e a l f o r m e d i u m s i z e d m i x e d v o i c e / d a t a s w i t c h a n d v o i c e p r o c e s s i n g a p p l i c a t i o n s . f i g u r e 1 - f u n c t i o n a l b l o c k d i a g r a m s t o 0 s t o 1 s t o 2 s t o 3 s t o 4 s t o 5 s t o 6 s t o 7 s e r i a l t o p a r a l l e l c o n v e r t e r d a t a m e m o r y f r a m e c o u n t e r c o n t r o l r e g i s t e r c o n t r o l i n t e r f a c e o u t p u t m u x c o n n e c t i o n m e m o r y p a r a l l e l t o s e r i a l c o n v e r t e r c s r / w a 5 / a 0 d t a d 7 / d 0 c s t o c 4 i f 0 i o d e s t i 0 s t i 1 s t i 2 s t i 3 s t i 4 s t i 5 s t i 6 s t i 7 d s d s 5 1 9 4 i s s u e 2 s e p t e m b e r 1 9 9 9 m t 8 9 l 8 5 e n h a n c e d d i g i t a l s w i t c h c m o s s t - b u s ? f a m i l y o r d e r i n g i n f o r m a t i o n m t 8 9 l 8 5 a p 4 4 p i n p l c c m t 8 9 l 8 5 a n 4 8 p i n s s o p - 4 0 c t o + 8 5 c a d v a n c e i n f o r m a t i o n r e s e t * * f o r 4 8 - p i n s s o p o n l y v d d v s s * *
MT89L85 advance information 2 figure 2 - pin connections pin description pin # name description 44 plcc 48 ssop 22 dt a data acknowledgment (open drain output) . this active low output indicates that a data bus transfer is complete. a pull-up resistor is required at this output. 3-5 7-11 3-5 7-11 sti0- sti7 st-bus input 0 to 7 (inputs). serial data input streams. these streams have 32 channels at data rates of 2.048 mbit/s. 12 12,36 v dd +3.3 volt power supply . 13 reset device reset (5v-tolerant input) . this pin is only available for the 48-pin ssop package. this active low input puts the MT89L85 in its reset state. it clears the internal counters anf registers. all st-bus outputs are set to the high impedance state. this reset pin must be held low for a minimum of 100nsec to reset the device. 13 14 f0i frame pulse (input). this input accepts and automatically identi?es frame synchronization signals formatted according to different backplane speci?cations such as st-bus and gci. 14 15 c4i clock (input). 4.096 mhz serial clock for shifting data in and out of the data streams. 15-17 19-21 16-18 20-22 a0-a5 address 0 to 5 (inputs). these lines provide the address to MT89L85 internal registers. 22 23 ds data strobe (input). this is the input for the active high data strobe on the microprocessor interface. this input operates with cs to enable the internal read and write generation. (jedec mo-118, 300mil wide) 1 6 5 4 3 2 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 32 31 30 23 18 19 20 21 22 24 25 26 27 28 17 29 sti3 sti4 sti5 sti6 sti7 v dd f0i c4i a0 a1 a2 sto3 sto4 sto5 sto6 sto7 v ss d0 d1 d2 d3 d4 nc sti1 dta ode sto1 nc nc a4 ds cs d6 nc a3 a5 r/ w d7 d5 44 pin plcc sti2 sti0 csto sto0 sto2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 48 pin ssop 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ode sto0 sto1 sto2 nc sto3 sto4 sto5 sto6 sto7 v ss v dd d0 d1 d2 d3 d4 nc d5 d6 dta sti0 sti1 sti2 nc sti3 sti4 sti5 sti6 sti7 v dd reset f0i c4i a0 a1 a2 nc a3 a4 48 csto v ss 21 27 d7 a5 22 26 cs ds 23 25 v ss r/ w 24
a d v a n c e i n f o r m a t i o n m t 8 9 l 8 5 3 2 3 2 4 r / w r e a d / w r i t e ( i n p u t ) . t h i s i n p u t c o n t r o l s t h e d i r e c t i o n o f t h e d a t a b u s l i n e s ( d 0 - d 7 ) d u r i n g a m i c r o p r o c e s s o r a c c e s s . 2 4 2 6 c s c h i p s e l e c t ( i n p u t ) . a c t i v e l o w i n p u t e n a b l i n g a m i c r o p r o c e s s o r r e a d o r w r i t e o f c o n t r o l r e g i s t e r o r i n t e r n a l m e m o r i e s . 2 5 - 2 7 2 9 - 3 3 2 7 - 2 9 3 1 - 3 5 d 7 - d 0 d a t a b u s 7 t o 0 ( b i d i r e c t i o n a l ) . t h e s e p i n s p r o v i d e m i c r o p r o c e s s o r a c c e s s t o d a t a i n t h e i n t e r n a l c o n t r o l r e g i s t e r , c o n n e c t m e m o r y h i g h , c o n n e c t m e m o r y l o w a n d d a t a m e m o r y . 3 4 1 , 2 5 , 3 7 v s s g r o u n d r a i l . 3 5 - 3 9 4 1 - 4 3 3 8 - 4 2 4 4 - 4 6 s t o 7 - s t o 0 s t - b u s o u t p u t s 7 t o 0 ( t h r e e - s t a t e o u t p u t s ) . s e r i a l d a t a o u t p u t s t r e a m s . t h e s e s t r e a m s a r e c o m p o s e d o f 3 2 c h a n n e l s a t d a t a r a t e s o f 2 . 0 4 8 m b i t / s . 4 4 4 7 o d e o u t p u t d r i v e e n a b l e ( i n p u t ) . t h i s i s a n o u t p u t e n a b l e f o r t h e s t o 0 t o s t o 7 s e r i a l o u t p u t s . i f t h i s i n p u t i s l o w s t o 0 - 7 a r e h i g h i m p e d a n c e . i f t h i s i n p u t i s h i g h e a c h c h a n n e l m a y s t i l l b e p u t i n t o h i g h i m p e d a n c e b y s o f t w a r e c o n t r o l . 1 4 8 c s t o c o n t r o l s t - b u s o u t p u t ( o u t p u t ) . t h i s o u t p u t i s a 2 . 0 4 8 m b / s l i n e w h i c h c o n t a i n s 2 5 6 b i t s p e r f r a m e . t h e l e v e l o f e a c h b i t i s c o n t r o l l e d b y t h e c o n t e n t s o f t h e c s t o b i t i n t h e c o n n e c t m e m o r y h i g h l o c a t i o n s . 6 , 1 8 , 2 8 , 4 0 6 , 1 9 , 3 0 , 4 3 n c n o c o n n e c t i o n . p i n d e s c r i p t i o n p i n # n a m e d e s c r i p t i o n 4 4 p l c c 4 8 s s o p f u n c t i o n a l d e s c r i p t i o n w i t h t h e i n t e g r a t i o n o f v o i c e , v i d e o a n d d a t a s e r v i c e s i n t o t h e s a m e n e t w o r k , t h e r e h a s b e e n a n i n c r e a s i n g d e m a n d f o r s y s t e m s w h i c h e n s u r e t h a t d a t a a t n x 6 4 k b i t / s r a t e s m a i n t a i n f r a m e s e q u e n c e i n t e g r i t y w h i l e b e i n g t r a n s p o r t e d t h r o u g h t i m e s l o t i n t e r c h a n g e c i r c u i t s . e x i s t i n g r e q u i r e m e n t s d e m a n d t i m e s l o t i n t e r c h a n g e d e v i c e s p e r f o r m i n g s w i t c h i n g w i t h c o n s t a n t t h r o u g h p u t d e l a y w h i l e g u a r a n t e e i n g m i n i m u m d e l a y f o r v o i c e c h a n n e l s . t h e m t 8 9 l 8 5 d e v i c e p r o v i d e s b o t h f u n c t i o n s a n d a l l o w s e x i s t i n g s y s t e m s b a s e d o n t h e m t 8 9 8 5 t o b e e a s i l y u p g r a d e d t o m a i n t a i n t h e d a t a i n t e g r i t y w h i l e m u l t i p l e c h a n n e l d a t a a r e t r a n s p o r t e d . t h e d e v i c e i s d e s i g n e d t o s w i t c h 6 4 k b i t / s p c m o r n x 6 4 k b i t / s d a t a . t h e m t 8 9 l 8 5 c a n p r o v i d e b o t h f r a m e i n t e g r i t y f o r d a t a a p p l i c a t i o n s a n d m i n i m u m t h r o u g h p u t s w i t c h i n g d e l a y f o r v o i c e a p p l i c a t i o n s o n a p e r c h a n n e l b a s i s . m i c r o p r o c e s s o r c a n a c c e s s i n p u t a n d o u t p u t t i m e s l o t s o n a p e r c h a n n e l b a s i s t o c o n t r o l d e v i c e s s u c h c e p t t r u n k i n t e r f a c e s t h r o u g h t h e s t - b u s i n t e r f a c e . d i f f e r e n t d i g i t a l b a c k p l a n e s c a n b e a c c e p t e d b y t h e m t 8 9 l 8 5 d e v i c e w i t h o u t u s e r ' s i n t e r v e n t i o n . t h e m t 8 9 l 8 5 d e v i c e p r o v i d e s a n i n t e r n a l c i r c u i t t h a t a u t o m a t i c a l l y i d e n t i e s t h e p o l a r i t y a n d f o r m a t o f f r a m e s y n c h r o n i z a t i o n i n p u t s i g n a l s c o m p a t i b l e t o s t - b u s a n d g c i i n t e r f a c e s . d e v i c e o p e r a t i o n a f u n c t i o n a l b l o c k d i a g r a m o f t h e m t 8 9 l 8 5 d e v i c e i s s h o w n i n f i g u r e 1 . t h e s e r i a l s t - b u s s t r e a m s o p e r a t e c o n t i n u o u s l y a t 2 . 0 4 8 m b / s a n d a r e a r r a n g e d i n 1 2 5 m s w i d e f r a m e s e a c h c o n t a i n i n g 3 2 8 - b i t c h a n n e l s . e i g h t i n p u t ( s t i 0 - 7 ) a n d e i g h t o u t p u t ( s t o 0 - 7 ) s e r i a l s t r e a m s a r e p r o v i d e d i n t h e m t 8 9 l 8 5 d e v i c e a l l o w i n g a c o m p l e t e 2 5 6 x 2 5 6 c h a n n e l n o n - b l o c k i n g s w i t c h m a t r i x t o b e c o n s t r u c t e d . t h e s e r i a l i n t e r f a c e c l o c k f o r t h e d e v i c e i s 4 . 0 9 6 m h z , a s r e q u i r e d i n s t - b u s a n d g c i s p e c i c a t i o n s . d a t a m e m o r y t h e r e c e i v e d s e r i a l d a t a i s c o n v e r t e d t o p a r a l l e l f o r m a t b y t h e o n - c h i p s e r i a l t o p a r a l l e l c o n v e r t e r s a n d s t o r e d s e q u e n t i a l l y i n a 2 5 6 - p o s i t i o n d a t a m e m o r y . t h e s e q u e n t i a l a d d r e s s i n g o f t h e d a t a m e m o r y i s g e n e r a t e d b y a n i n t e r n a l c o u n t e r t h a t i s r e s e t b y t h e i n p u t 8 k h z f r a m e p u l s e ( f 0 i ) m a r k i n g t h e f r a m e b o u n d a r i e s o f t h e i n c o m i n g s e r i a l d a t a s t r e a m s . d e p e n d i n g o n t h e t y p e o f i n f o r m a t i o n t o b e s w i t c h e d , t h e m t 8 9 l 8 5 d e v i c e c a n b e p r o g r a m m e d t o p e r f o r m b y u s i n g z a r l i n k m e s s a g e m o d e c a p a b i l i t y , t h e a s t h e z a r l i n k m t 8 9 7 2 , i s d n t r a n s c e i v e r s a n d t 1 /
MT89L85 advance information 2-4 time slot interchange functions with different throughput delay capabilities on a per-channel basis. for voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. in multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch. data to be output on the serial streams may come from two sources: data memory or connect memory. locations in the connect memory, which is split into high and low parts, are associated with particular st-bus output streams. when a channel is due to be transmitted on an st-bus output, the data for the channel can either be switched from an st-bus input (connection mode) or it can be originated from the microprocessor (message mode). if a channel is con?gured in connection mode, the source of the output data is the data memory. if a channel is con?gured in message mode, the source of the output data is the connect memory low. data destined for a particular channel on the serial output stream is read from the data or connect memory low during the previous channel time slot. this allows enough time for memory access and internal parallel to serial conversion. connection and message modes in connection mode, the addresses of input source for all output channels are stored in the connect memory low. the connect memory low locations are mapped to each location corresponding to an output 64 kb/s channel. the contents of the data memory at the selected address are then transferred to the parallel to serial converters. by having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. in message mode the cpu writes data to the connect memory low locations which correspond to the output link and channel number. the contents of the connect memory low are transferred to the parallel to serial converter one channel before it is to be output. the connect memory low data is transmitted each frame to the output until it is changed by the cpu. the per-channel functions available in the MT89L85 are controlled by the connect memory high bits, which determine whether individual output channels are selected into speci?c conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. in addition, the connect memory high provides one bit to allow the user to control the state of the csto output pin. if an output channel is set to three-state condition, the tdm serial stream output will be placed in high impedance during that channel time. in addition to the per-channel three-state control, all channels on the tdm outputs can be placed in high impedance at one time by pulling the ode input pin in low. this overrides the individual per-channel programming on the connect memory high bits. the connect memory data is received via the microprocessor interface at d0-d7 lines. the addressing of the MT89L85 internal registers, data and connect memories is performed through address input pins and some bits of the device's control register. the higher order address bits come from the control register, which may be written or read through the microprocessor interface. the lower order address bits come directly from the external address line inputs. for details on the device addressing, see software control and control register description. serial interface timing the MT89L85 master clock ( c4i) is a 4.096 mhz allowing serial data link con?guration at 2.048 mb/s to be implemented. the MT89L85 frame synchronization pulse can be formatted according to st-bus or gci interface speci?cations; i.e., the frame pulse can be active in high (gci) or low (st-bus). the MT89L85 device automatically detects the presence of an input frame pulse and identi?es the type of backplane present on the serial interface. upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. in st-bus mode, every second falling edge of the 4.096 mhz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. in gci mode, every second rising edge of the 4.096 mhz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. dela y through the MT89L85 the transfer of information from the input serial streams to the output serial streams results in a delay through the MT89L85 device. the delay through the device varies according to the mode selected in the v/c bit of the connect memory high.
a d v a n c e i n f o r m a t i o n m t 8 9 l 8 5 2 - 5 v a r i a b l e d e l a y m o d e t h e d e l a y i n t h i s m o d e i s d e p e n d e n t o n l y o n t h e c o m b i n a t i o n o f s o u r c e a n d d e s t i n a t i o n c h a n n e l s a n d i t i s n o t d e p e n d e n t o n t h e i n p u t a n d o u t p u t s t r e a m s . t h e m i n i m u m d e l a y a c h i e v a b l e i n t h e m t 8 9 l 8 5 d e v i c e i s 3 t i m e s l o t s . i n t h e m t 8 9 l 8 5 d e v i c e , t h e i n f o r m a t i o n t h a t i s t o b e o u t p u t i n t h e s a m e c h a n n e l p o s i t i o n a s t h e i n f o r m a t i o n i s i n p u t ( p o s i t i o n n ) , r e l a t i v e t o f r a m e p u l s e , w i l l b e o u t p u t i n t h e f o l l o w i n g f r a m e ( c h a n n e l n , f r a m e n + 1 ) . t h e s a m e o c c u r s i f t h e i n p u t c h a n n e l h a s t o b e o u t p u t i n t h e t w o c h a n n e l s s u c c e e d i n g ( n + 1 a n d n + 2 ) t h e c h a n n e l p o s i t i o n a s t h e i n f o r m a t i o n i s i n p u t . t h e i n f o r m a t i o n s w i t c h e d t o t h e t h i r d t i m e s l o t a f t e r t h e i n p u t h a s e n t e r e d t h e d e v i c e ( f o r i n s t a n c e , i n p u t c h a n n e l 0 t o o u t p u t c h a n n e l 3 o r i n p u t c h a n n e l 3 0 t o o u t p u t c h a n n e l 1 ) , i s a l w a y s o u t p u t t h r e e c h a n n e l s l a t e r . a n y s w i t c h i n g c o n g u r a t i o n t h a t p r o v i d e s t h r e e o r m o r e t i m e s l o t s b e t w e e n i n p u t a n d o u t p u t c h a n n e l s , w i l l h a v e a t h r o u g h p u t d e l a y e q u a l t o t h e d i f f e r e n c e b e t w e e n t h e o u t p u t a n d i n p u t c h a n n e l s ; i . e . , t h e t h r o u g h p u t d e l a y w i l l b e l e s s t h a n o n e f r a m e . t a b l e 1 s h o w s t h e p o s s i b l e d e l a y s f o r t h e m t 8 9 l 8 5 d e v i c e i n v a r i a b l e d e l a y m o d e : t a b l e 1 - c h a n n e l d e l a y f o r t h e v a r i a b l e d e l a y m o d e c o n s t a n t d e l a y m o d e i n t h i s m o d e f r a m e i n t e g r i t y i s m a i n t a i n e d i n a l l s w i t c h i n g c o n g u r a t i o n s b y m a k i n g u s e o f a m u l t i p l e d a t a - m e m o r y b u f f e r t e c h n i q u e w h e r e i n p u t c h a n n e l s w r i t t e n i n a n y o f t h e b u f f e r s d u r i n g f r a m e n w i l l b e r e a d o u t d u r i n g f r a m e n + 2 . i n t h e m t 8 9 l 8 5 , t h e m i n i m u m t h r o u g h p u t d e l a y a c h i e v e - a b l e i n c o n s t a n t d e l a y m o d e w i l l b e 3 2 t i m e s l o t s ; f o r e x a m p l e , w h e n i n p u t t i m e s l o t 3 2 ( c h a n n e l 3 1 ) i s s w i t c h e d t o o u t p u t t i m e s l o t 1 ( c h a n n e l 0 ) . l i k e w i s e , t h e m a x i m u m d e l a y i s a c h i e v e d w h e n t h e r s t t i m e s l o t i n a f r a m e ( c h a n n e l 0 ) i s s w i t c h e d t o t h e l a s t t i m e s l o t i n t h e f r a m e ( c h a n n e l 3 1 ) , r e s u l t i n g i n 9 4 t i m e s l o t s o f d e l a y . i n p u t c h a n n e l o u t p u t c h a n n e l t h r o u g h p u t d e l a y n m = n , n + 1 o r n + 2 m - n + 3 2 t i m e s l o t s n m > n + 2 m - n t i m e s l o t s n m < n 3 2 - ( n - m ) t i m e s l o t s t o s u m m a r i z e , a n y i n p u t t i m e s l o t f r o m i n p u t f r a m e n w i l l b e a l w a y s s w i t c h e d t o t h e d e s t i n a t i o n t i m e s l o t o n o u t p u t f r a m e n + 2 . i n c o n s t a n t d e l a y m o d e , t h e d e v i c e t h r o u g h p u t d e l a y i s c a l c u l a t e d a c c o r d i n g t o t h e f o l l o w i n g f o r m u l a : d e l a y = [ 3 2 + ( 3 2 - i n ) + ( o u t - 1 ) ] ; ( e x p r e s s e d i n n u m b e r o f t i m e s l o t s ) w h e r e : i n i s t h e n u m b e r o f t h e i n p u t t i m e s l o t ( f r o m 1 t o 3 2 ) . o u t i s t h e n u m b e r o f t h e o u t p u t t i m e s l o t ( f r o m 1 t o 3 2 ) . m i c r o p r o c e s s o r p o r t t h e m t 8 9 l 8 5 m i c r o p r o c e s s o r p o r t h a s p i n d e v i c e s p r o v i d i n g a n o n - m u l t i p l e x e d b u s a r c h i t e c t u r e . t h e p a r a l l e l p o r t c o n s i s t s o f a n 8 b i t p a r a l l e l d a t a b u s ( d 0 - d 7 ) , s i x a d d r e s s i n p u t l i n e s ( a 0 - a 5 ) a n d f o u r c o n t r o l l i n e s ( c s , d s , r / w a n d d t a ) . t h i s p a r a l l e l m i c r o p o r t a l l o w s t h e a c c e s s t o t h e c o n t r o l r e g i s t e r s , c o n n e c t i o n m e m o r y h i g h , c o n n e c t i o n m e m o r y l o w a n d t h e d a t a m e m o r y . a l l l o c a t i o n s a r e r e a d / w r i t t e n e x c e p t f o r t h e d a t a m e m o r y w h i c h c a n b e r e a d o n l y . a c c e s s e s f r o m t h e m i c r o p o r t t o t h e c o n n e c t i o n m e m o r y a n d t h e d a t a m e m o r y a r e m u l t i p l e x e d w i t h a c c e s s e s f r o m t h e i n p u t a n d o u t p u t t d m p o r t s . t h i s c a n c a u s e v a r i a b l e d a t a a c k n o w l e d g e d e l a y s ( d t a ) . f i g u r e 3 - a d d r e s s m e m o r y m a p n o t e : " x " d o n t c a r e s o f t w a r e c o n t r o l t h e a d d r e s s l i n e s o n t h e m i c r o p r o c e s s o r i n t e r f a c e g i v e a c c e s s t o t h e m t 8 9 l 8 5 i n t e r n a l r e g i s t e r s a n d m e m o r i e s . i f t h e a 5 , a 1 , a 0 a d d r e s s l i n e i n p u t s a r e l o w , t h e n t h e m t 8 9 l 8 5 i n t e r n a l c o n t r o l r e g i s t e r i s a d d r e s s e d ( s e e f i g u r e 3 ) . i f a 5 i n p u t l i n e i s h i g h , t h e n t h e r e m a i n i n g a d d r e s s i n p u t l i n e s a r e u s e d t o s e l e c t m e m o r y s u b s e c t i o n s o f 3 2 l o c a t i o n s c o r r e s p o n d i n g t o t h e n u m b e r o f c h a n n e l s p e r i n p u t o r o u t p u t s t r e a m . a s e x p l a i n e d i n t h e c o n t r o l r e g i s t e r a 5 a 4 a 3 a 2 a 1 a 0 l o c a t i o n 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 c o n t r o l r e g i s t e r c h a n n e l 0 c h a n n e l 1 c h a n n e l 3 1 c o m p a t i b i l i t y w i t h z a r l i n k m t 8 9 8 5 d i g i t a l s w i t c h
MT89L85 advance information 6 figure 4 - control register bits x = dont care bit name description 7 sm split memory. when 1, all subsequent reads are from the data memory and writes are to the connection memory low, except when the control register is accessed again. the memory select bits need to be set to specify the memory for the operations. when 0, the memory select bits specify the memory for subsequent operations. in either case, the stream address bits select the subsection of the memory which is made available. 6 me message enable. when 1, the contents of the connection memory low are output on the serial output streams except when in high impedance. when 0, the connection memory bits for each channel determine what is output. 4-3 ms1-ms0 memory select bits. the memory select bits operate as follows: 0-0 - not to be used 0-1 - data memory (read only from the cpu) 1-0 - connection memory low 1-1 - connection memory high 2-0 sta2-0 stream address bits 2-0. the number expressed in binary notation on these bits refers to the input or output st-bus stream which corresponds to the subsection of memory made accessible for subsequent operations. sm me x ms1 ms0 sta2 sta1 sta0 76543210 description, the address input lines and the stream address bits (sta) of the control register give the user the capability of selecting all positions of the MT89L85 data and connect memories. the data in the control register consists of split memory and message mode bits, memory select and stream address bits (see figure 4). the memory select bits allow the connect memory high or low or the data memory to be chosen, and the stream address bits de?ne an internal memory subsections corresponding to input or output st-bus streams. bit 7 (split memory) of the control register allows split memory operation whereby reads are from the data memory and writes are to the connect memory low. the message enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the connect memory low (cml) are output on the st-bus output streams once every frame unless the ode input pin is low. if me bit is high, then the MT89L85 behaves as if bits 2 (message channel) and 0 (output enable) of every connect memory high (cmh) locations were set to high, regardless of the actual value. if me bit is low, then bit 2 and 0 of each connect memory high location operates normally. in this case, if bit 2 of the cmh is high, the associated st-bus output channel is in message mode. if bit 2 of the cmh is low, then the contents of the cml de?ne the source information (stream and channel) of the time slot that is to be switched to an output. if the ode input pin is low, then all serial outputs are high-impedance. if ode is high, then bit 0 (output enable) of the cmh location enables (if high) or disables (if low) the output drivers for the corresponding individual st-bus output stream and channel. the contents of bit 1 (csto) of each connection memory high location (see figure 5) is output on csto pin once every frame. the csto pin is a 2048 mbit/s output which carries 256 bits. if csto bit is set high, the corresponding bit on csto output is transmitted in high. if csto bit is low, the corresponding bit on the csto output is transmitted in low. the contents of the 256 csto bits of the cmh are transmitted sequentially on to the csto output pin and are synchronous to the st-bus streams. to allow for delay in any external control
advance information MT89L85 7 figure 5 - connection memory high bits x = dont care figure 6 - connection memory low bits bit name description 6 v/c variable/constant throughput delay mode. this bit is used to select between variable (low) and constant delay (high) modes on a per-channel basis. 2 mc message channel. when 1, the contents of the corresponding location in connection memory low are output on the corresponding channel and stream. when 0, the contents of the programmed location in connection memory low act as an address for the data memory and so determine the source of the connection to the locations channel and stream. 1 csto csto bit. this bit drives a bit time on the csto output pin. 0 oe output enable. this bit enables the output drivers on a per-channel basis. this allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. a high enables the driver and a low disables it. bit name description 7-5 sab2-0* source stream address bits. these three bits are used to select eight source streams for the connection. bit 7 of each word is the most signi?cant bit. 4-0* cab4-0* source channel address bits 0-4. these ?ve bits are used to select 32 different source channels for the connection (the st-bus stream where the channel is present is de?ned by bits sab2-0). bit 4 is the most signi?cant bit. * if bit 2 of the corresponding connection high location is 1 or if bit 6 of the control register is 1, then these entire 8 bits are output on the channel and stream associated with this location. otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. x v/c x x x mc csto oe 76543210 sab2 sab1 sab0 cab4 cab3 cab2 cab1 cab0 76543210 circuitry the contents of the csto bit is output one channel before the corresponding channel on the st- bus streams. for example, the contents of csto bit in position 0 (st0, ch0) of the cmh, is transmitted synchronously with st-bus channel 31, bit 7. the contents of csto bit in position 32 (st1, ch0) of the cmh is transmitted during st-bus channel 31 bit 6. bit v/c (variable/constant delay) on the connect memory high locations allow per-channel selection between variable and constant throughput delay capabilities. initialization of the MT89L85 on initialization or power up, the contents of the connection memory high can be in any state. this is a potentially hazardous condition when multiple MT89L85 st-bus outputs are tied together to form matrices, as these outputs may con?ict. the ode pin should be held low on power up to keep all outputs in the high impedance condition.
MT89L85 advance information 8 figure 7 - typical exchange, pbx or multiplexer con?guration s/u basic rate line card mt8930/31 mt8910 mt8972 st-bus to other lines layers 2 & 3 entity mt8940/ mt8941 routing matrix MT89L85s mh89760/ mh89790 mt8920 m c st-bus st-bus t1/e1 link to other lines primary rate card c p u during the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. care should be taken that no two connected st-bus outputs drive the bus simultaneously. when this process is complete, the microprocessor controlling the matrices can bring the ode signal high to relinquish high impedance state control to the cmh b 0s. applications typical exchange, pbx or multiplexer figure 7 shows a typical implementation of line cards being interconnected through a central routing matrix that can scale up in channel capacity to accommodate different number of ports depending on the application. in a con?guration where the switched services utilize concatenated or grouped time slots to carry voice, data and video (channels of 128, 256 kb/s, isdn h0 and others), the central routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. figure 7 shows an example where the MT89L85 device guarantees data integrity when data ?ows from the t1/e1 to the s/u interface links and vice-versa. modern technologies available today such as frame relay network using dedicated fractional t1 are one of the key applications for the MT89L85 device. low latency isochronous network in today's local working group environment, there is an increasing demand for solutions on interconnection of desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable network allowing the deployment of multimedia services. existing multimedia applications require a network with
a d v a n c e i n f o r m a t i o n m t 8 9 l 8 5 9 f i g u r e 8 a - p r i v a t e i s o c h r o n o u s n e t w o r k a c c e s s t o p u b l i c n e t w o r k a n a l o g c o n n e c t i o n s i s d n d e s k t o p s n x 6 4 c o n n e c t i o n s ( e . g . v i d e o ) i s o c h r o n o u s n e t w o r k s e r v e r 1 s e r v e r 2 s e r v e r 3 s e r v e r 4 t 1 t 1 e 1 t 1 / e 1 ( 2 b + d ) p r e d i c t a b l e d a t a t r a n s f e r d e l a y s t h a t c a n b e i m p l e m e n t e d a t a r e a s o n a b l e c o s t . t h e l o w l a t e n c y i s o c h r o n o u s n e t w o r k i s o n e o f t h e a l t e r n a t i v e s t h a t s y s t e m d e s i g n e r s h a v e c h o s e n t o a c c o m m o d a t e t h i s r e q u i r e m e n t ( s e e f i g u r e 8 a ) . t h i s n e t w o r k c a n b e i m p l e m e n t e d u s i n g e x i s t i n g t d m t r a n s m i s s i o n m e d i a d e v i c e s s u c h a s i s d n b a s i c ( s o r u ) a n d p r i m a r y r a t e s t r u n k s ( t 1 a n d c e p t ) t o t r a n s p o r t m i x e d v o i c e a n d d a t a s i g n a l s i n g r o u p e d t i m e s l o t s ; f o r e x a m p l e , 2 b c h a n n e l s i n c a s e o f i s d n s o r u i n t e r f a c e s o r u p t o 3 2 c h a n n e l s i n c a s e o f a c e p t l i n k . f i g u r e 8 b s h o w s a m o r e d e t a i l e d c o n g u r a t i o n w h e r e b y s e v e r a l p c s a r e c o n n e c t e d t o f o r m a n i s o c h r o n o u s n e t w o r k . s e v e r a l s e r v i c e s c a n b e i n t e r c o n n e c t e d w i t h i n a s i n g l e p c c h a s s i s t h r o u g h t h e s t a n d a r d i z e d m u l t i v e n d o r i n t e g r a t i o n p r o t o c o l ( m v i p ) . s u c h a n i n t e r f a c e a l l o w s t h e d i s t r i b u t i o n a n d i n t e r c o n n e c t i o n o f s e r v i c e s l i k e v o i c e m a i l , i n t e g r a t e d v o i c e r e s p o n s e , v o i c e r e c o g n i t i o n , l a n g a t e w a y s , k e y s y s t e m s , f a x s e r v e r s , v i d e o c a r d s , e t c . t h e i n f o r m a t i o n b e i n g e x c h a n g e d b e t w e e n c a r d s t h r o u g h t h e m v i p i n t e r f a c e o n e v e r y c o m p u t e r a s w e l l a s b e t w e e n c o m p u t e r s t h r o u g h t 1 o r c e p t l i n k s i s , i n g e n e r a l , o f m i x e d t y p e w h e r e 6 4 k b / s a n d n * 6 4 k b / s c h a n n e l s a r e g r o u p e d t o g e t h e r . w h e n s u c h a m i x e d t y p e o f d a t a i s t r a n s f e r r e d b e t w e e n c a r d s w i t h i n o n e c h a s s i s o r f r o m o n e c o m p u t e r t o a n o t h e r , t h e s e q u e n c e i n t e g r i t y o f t h e c o n c a t e n a t e d c h a n n e l s h a s t o b e m a i n t a i n e d . t h e m t 8 9 l 8 5 d e v i c e s u i t s t h i s a p p l i c a t i o n a n d c a n b e u s e d t o f o r m a c o m p l e t e n o n - b l o c k i n g s w i t c h m a t r i x o f 5 1 2 c h a n n e l s ( s e e f i g u r e 9 ) . t h i s a l l o w s 8 p a i r s o f s t - b u s s t r e a m s t o b e d e d i c a t e d t o t h e m v i p s i d e w h e r e a s t h e r e m a i n i n g 8 p a i r s a r e u s e d f o r l o c a l a n c i l l i a r y f u n c t i o n s i n t y p i c a l d u a l t 1 / e 1 i n t e r f a c e a p p l i c a t i o n s ( f i g u r e 1 0 ) . a n o t h e r a p p l i c a t i o n o f t h e m t 8 9 l 8 5 i n a n m v i p e n v i r o n m e n t i s t o b u i l d a n i s d n s - i n t e r f a c e c a r d ( f i g u r e 1 1 ) . i n t h i s c a r d , 7 p a i r s o f s t - b u s s t r e a m s a r e c o n n e c t e d t o t h e m v i p i n t e r f a c e w h i l e t h e r e m a i n i n g p a i r i s r e s e r v e d f o r t h e i n t e r c o n n e c t i o n o f z a r l i n k m t 8 9 3 0 ( s n i c ) , m t 8 9 9 2 ( h - p h o n e ) a n d t h e m v i p i n t e r f a c e .
m t 8 9 l 8 5 a d v a n c e i n f o r m a t i o n 1 0 f i g u r e 8 b - i m p l e m e n t a t i o n o f a n i s o c h r o n o u s n e t w o r k u s i n g z a r l i n k c o m p o n e n t s s e r v e r 1 m h 8 9 7 6 0 b m h 8 9 7 9 0 b s t - b u s m t 8 9 l 8 5 s ( x 4 ) m t 8 9 3 0 b m t 8 9 3 0 b m v i p b u s i s d n s - i n t e r f a c e l o c a l t 1 / e 1 l i n k m v i p b u s s e r v e r 3 ( 2 5 6 p o r t s w i t c h m o d u l e ) s e r v e r 3 m h 8 9 7 6 0 b / 7 9 0 b m h 8 9 7 6 0 b / 7 9 0 b m h 8 9 7 6 0 b / 7 9 0 b s t - b u s m t 8 9 l 8 5 s ( x 4 ) h d l c m t 8 9 l 8 5 m t 8 9 l 8 5 m t 8 9 l 8 5 m t 8 9 l 8 5 s t - b u s m h 8 9 7 6 0 b m h 8 9 7 9 0 b d u a l t 1 / e 1 c a r d m h 8 9 7 6 0 b m h 8 9 7 9 0 b m t 8 9 7 2 b o r a n a l o g m t 8 9 l 8 5 s ( x 4 ) s e r v e r 2 m v i p b u s s t - b u s t o v i d e o , d a t a , f a x s e r v i c e s l o c a l e n v i r o n m e n t n e t w o r k a c c e s s l o c a l t 1 / e 1 l i n k t 1 e 1 t o v i d e o , d a t a , f a x a n d o t h e r s e r v i c e s p u b l i c
advance information MT89L85 11 figure 9 - 512-channel switch array figure 10 - dual t1/e1 card functional block diagram 8 input streams from mvip 8 input on-board st-bus streams 8 output streams to mvip 8 output on-board st-bus streams mvip direction mvip enable MT89L85 #1 csto MT89L85 #2 csto MT89L85 #3 MT89L85 #4 fdl hdlc mt8952b t1/e1 mh89760b or mh89790b hdlc mt8952b analog d-phone mt8992/93 switch MT89L85 switch MT89L85 switch MT89L85 switch MT89L85 dpll mt8941 pc interface mvip header mvip sto0-7 mvip sti0-7 fdl hdlc mt8952b t1/e1 mh89760b or mh89790b hdlc mt8952b 512 channel switch matrix
MT89L85 advance information 12 figure 11 - s-access card functional block diagram mvip header switch matrix s interface hdlc digital phone dpll dtmf receiver pc interface hdlc sti7-1 sto7-1 sti0 sto0 mt8930b mt8941 mt8992/93 mt8870 mvip sti1-7 mvip sto1-7 MT89L85
advance information MT89L85 13 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * absolute maximum ratings* parameter symbol min max units 1v dd - v ss -0.3 5.0 v 2 voltage on digital inputs v i v ss -0.3 v dd +0.3 v 3 current at digital outputs i o 20 ma 4 storage temperature t s -55 +125 c 5 package power dissipation p d 1w recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 25 +85 c 2 positive supply v dd 3.0 3.3 3.6 v 3 input high voltage v ih 0.7v dd v dd v 4 input high voltage on 5v tolerant inputs v ih 5.5 v 5 input low voltage v il v ss 0.3v dd v dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 i n p u t s supply current i dd 4 7 ma outputs unloaded 2 input high voltage v ih 0.7v dd v 3 input low voltage v il 0.3v dd v 4 input leakage i il 5 m av i between v ss and v dd 5 input pin capacitance c i 10 pf 6 o u t p u t s output high voltage v oh 0.8v dd vi oh = 10 ma 7 output high current i oh 10 ma sourcing. v oh =0.8v dd 8 output low voltage v ol 0.4 v i ol = 5 ma 9 output low current i ol 5 ma sinking. v ol = 0.4v 10 high impedance leakage i oz 5 m av o between v ss and v dd 11 output pin capacitance c o 10 pf ac electrical characteristics _ timing parameter measurement voltage levels characteristics sym level units test conditions 1 cmos threshold voltage v tt 0.5v dd v 2 cmos rise/fall threshold voltage high v hm 0.7v dd v 3 cmos rise/fall threshold voltage low v lm 0.3v dd v
MT89L85 advance information 14 ? timing is over recommended temperature & power supply voltages (v dd =5v 5%, v ss =0v, t a =C40 to 85 c). ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 12 - st-bus timing ac electrical characteristics ? - st-bus timing voltages are with respect to ground (vss) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 frame pulse width t f0iw 244 ns 2 frame pulse setup time t f0is 10 190 ns 3 frame pulse hold time t f0ih 20 190 ns 4 sto delay active to active t saa 55 ns c l =150 pf 5 sti setup time t stis 20 ns 6 sti hold time t stih 20 ns 7 clock period t c4i 200 244 300 ns 8 ck input low t cl 85 122 150 ns 9 ck input high t ch 85 122 150 ns 10 clock rise/fall time t r, t f 10 ns v hm v lm sti v hm v lm v hm v lm sto v hm v lm f0i t f0iw t c4i t ch t cl t f0is t daa t stis t stih t f0ih ch. 31 bit 0 ch. 0 bit 7 ch. 0 bit 6 ch. 31 bit 0 ch. 0 bit 7 ch. 0 bit 6 ch. 0 bit 5 ch. 0 bit 5 c4i t f t r
advance information MT89L85 15 ? timing is over recommended temperature & power supply voltages (v dd =3.3v 5%, v ss =0v, t a =C40 to 85 c). ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 13 - gci timing ac electrical characteristics ? - gci timing voltages are with respect to ground (vss) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 clock period t c4i 150 244 300 ns 2 pulse width t cl , t ch 73 122 150 ns 3 frame width high t wfh 244 ns 4 frame setup t f0is 10 190 ns 5 frame hold t f0ih 20 190 ns 6 data delay/clock active to active t daa 55 ns c l =150 pf 7 serial input setup t stis 20 ns 8 serial input hold t stih 20 ns 9 clock rise/fall time t r, t f 10 ns v hm v lm sto v hm v lm c4i v hm v lm f0i c4i f0i sti/ sto bit 0 bit 1 bit 2 bit 3 see detail a detail a note: bit 0 identifies the first bit of the gci frame t cl t ch t c4i t daa t wfh t f0is t f0ih t stis t stih v hm v lm sti t f t r
MT89L85 advance information 16 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics ? - serial streams for st-bus and gci backplanes characteristics sym min typ ? max units test conditions 1 o u t p u t s sto0/7 delay - active to high z t saz 55 ns r l =1 k w * , c l =150 pf 2 sto0/7 delay - high z to active t sza 55 ns c l =150 pf 3 output driver enable delay t oed 50 ns r l =1 k w * , c l =150 pf 4 csto output delay t xcd 55 ns c l =150 pf figure 14 - serial outputs and external control c4i v hm v lm sto0 to sto7 v hm v lm sto0 to sto7 v hm v lm csto v hm v lm bit cell boundary (gci) (st-bus) * t saz t sza t xcd * figure 15 - output driver enable ode sto0 to sto7 v hm v lm v hm v lm t oed * * t oed
advance information MT89L85 17 ? timing is over recommended temperature & power supply voltages . ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 16 - motorola non-multiplexed bus timing ac electrical characteristics ? - microprocessor bus voltages are with respect to ground (vss) unless otherwise stated . characteristics sym min typ ? max units test conditions 1 cs setup from ds rising t css 0ns 2r/ w setup from ds rising t rws 5ns 3 add setup from ds rising t ads 5ns 4 cs hold after ds falling t csh 0ns 5r/ w hold after ds falling t rwh 5ns 6 add hold after ds falling t adh 8ns 7 data setup from dt a low on read t ddr 0ns c l =150 pf 8 data hold on read t dhr 10 90 ns r l =1 k w * , c l =150 pf 9 data setup on write (fast write) t dsw 025 ns 10 valid data delay on write (slow write) t swd 122 ns 11 data hold on write t dhw 510 ns 12 acknowledgment delay: reading data memory reading/writing conn. memory writing to control register reading control register t akd 560 62/30 25 52 1220 120/53 65 120 ns ns ns ns c l =150 pf 13 acknowledgment hold time t akh 50 80 ns r l =1 k w * , c l =150 pf ds cs r/ w a0-a6 d0-d7 read d0-d7 write dt a t css t rws t ads t csh t rwh t adh valid data t swd t dsw t dhr t ddr t akd t dhw t akh valid data v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm v hm v lm

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